Electronic systems and devices have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data in most areas of business, science, education and entertainment. These electronic systems typically include various components and scan testing the system components is often important for ensuring proper testing and debug. However, adding scan testing capabilities to a system can be complicated and also have undesirable impacts.
Some conventional systems include arrays of components. An array can be designed to include a structured data path. The data paths often have regular structures and are generally used for transporting data like wide busses. Data path blocks can be built with regular rows and columns of various components (e.g., flops, latches, adders, etc). Placement of the data paths is typically important and placement can impact the design or layout (e.g., the layout can become large, etc.). However, traditional array approaches that include structured data paths usually have some characteristics that present challenges for scan testing (e.g., challenges related to ATPG tools, diagnosibility, etc.). Traditional attempts at addressing these challenges are often problematic.
While scan testability typically has a variety of benefits it can also often have associated potential undesirable impacts. Adding scan testability can have detrimental impacts on timing and typically increases the size of the circuitry. There is usually a trade off between adding scan testability and the undesirable impacts. Leaving out or limiting scan test components typically leads to reduced ability to detect faults. In some conventional array data paths, a majority of undetected faults are due to the control portion (e.g., decoder for the write addresses, clock gates, clock lines, etc.). Some conventional arrays also include non scannable cells or elements (e.g., non scannable storage elements, non scannable latches, etc.) that also contribute to undetected faults.